1. Field of the Invention
The present invention generally relates to a liquid crystal display (LCD) panel and a method for manufacturing the same, and more particularly to a structure of a gate line and to an intersection portion of the gate line and a signal line.
2. Description of the Related Art
A conventional method for manufacturing an a-Si TFT liquid crystal display panel is described herein below with regard to a liquid crystal device portion. As shown in FIGS. 12(a) and 12(b), a gate electrode 4 and a gate line 5 connected thereto are first formed into a predetermined shape on a glass substrate 2 by a conventional technique. Then, as shown in FIG. 13, a gate insulating film 6, a channel layer 8 and a SiNx film 10, serving as an etching stopper layer, are successively stacked on the entire surface of the glass substrate 2. As shown in FIGS. 14(a) to 14(c), after coating a resist on the SiNx film 10, the glass substrate 2 is exposed to light from its back surface side by using the gate electrode 4 having a predetermined shape as a light shielding mask. Subsequently, the glass substrate 2 is subjected to stepper exposure from its front surface side by using a reticle, and then the resist is developed. Thereafter, the SiNx film 10, other than a portion functioning as an etching stopper (e.g., channel protecting film) 12, is etched with diluted hydrofluoric (HF) acid, and then the resist is removed.
As described above, the etching stopper 12 can be formed through a single exposing step in which the glass substrate 2 is subjected to the stepper exposure from its front surface side by using a reticle. However, in this conventional manufacturing method, the etching stopper 12 is formed through a two-stage exposure. The stages include exposing the substrate 2 to light from its back surface side and exposing the substrate 2 to light from its front surface side.
This approach is used because, when the etching stopper 12 is formed through a single-stage exposing step in which the glass substrate 2 is exposed to light from its front surface side, the alignment with the gate electrode 4 tends to be shifted and cannot be stabilized.
In contrast, if the gate electrode 4 is effectively used in the two-stage exposing step, the etching stopper 12 is disposed at the center of the gate electrode 4 in a self-aligned manner. Referring to FIG. 15, this provides a source electrode 26 and a drain electrode 28 symmetrically positioned about the gate electrode 4, and also reduces overlap areas between the gate electrode 4 and the drain electrode 28 and between the gate electrode 4 and the source electrode 26. Thus, the two-stage exposure can improve a transistor""s characteristic.
However, in manufacturing a liquid crystal display panel, there are many complicated, time-consuming steps. Therefore, reducing the number of processes not only improves productivity, but also reduces the manufacturing cost of a LCD panel in which the process cost accounts for a large proportion of the total cost.
After being developed, the resist for forming the etching stopper 12 has a size of approximately 20xc3x9710 xcexcm per pixel, and such rectangular resists are arranged side-by-side over the entire surface of an array substrate. Since the area of each resist is relatively small, its adhesion to the underlying nitride film (e.g., the SiNx film) is low, and hence, the resist is apt to be easily peeled-off. When the resist is peeled-off, the etching stopper 14 cannot be properly formed, which leads to transistor failure.
When the etching stopper layer 10 is etched with diluted hydrofluoric acid, the etching stopper layer 10 is generally over-etched so as not to leave an insufficiently etched portion. However, excessive overetching causes the side surface of the etching stopper 12 to be inclined inward at the foot thereof, thereby resulting in the formation of a xe2x80x9cconcavityxe2x80x9d 15 (which is hidden in a top view), as shown in FIG. 14(c). When films (and/or foreign matter) to be deposited in subsequent steps are attached to the concavity 15, they cannot be removed through cleaning and etching. As a result, as shown in FIG. 15, a leakage current flows between the source electrode 26 and the drain electrode 28 formed on the etching stopper 12, which leads to a leakage failure of the transistor.
In an attempt to overcome the above disadvantages, in Japanese Patent Application No. 10-278689 the present inventors developed a novel method for manufacturing a liquid crystal display panel, which includes a single exposing step by using a gate electrode and a gate line as shielding masks.
However, in the above manufacturing method, the etching stopper layer 12 is not removed from an intersection portion of the gate line where the gate line and the signal line intersect each other. If the etching stopper layer is not removed from the intersection portion, etching solution may easily penetrate into the intersection portion during an etching process, and thus an open defect of the signal line may be latently induced.
In view of the foregoing and other problems, drawbacks, and disadvantages of the conventional methods, it is an object of the present invention to provide a structure and method for removing an etching stopper layer on an intersection portion of a gate line where the gate line and a signal line intersect each other without using an additional exposing step.
It is another object of the present invention that an etching stopper be formed through only a single exposing step by using a gate electrode and a gate line as shielding masks in the method for manufacturing a liquid crystal display panel. Reducing of the number of steps, especially the number of exposing steps, contributes to productivity improvements and a reduction of the manufacturing cost.
In a first aspect, a liquid crystal display panel according to the present invention includes two or more conductive portions and one or more opening portions on an intersection portion of a gate line where the gate line and a signal line intersect each other. The gate line and the signal line output electrical signals to a liquid crystal device arranged in a matrix pattern. Since the etching stopper layer is removed from the intersection portion having opening portions, penetration of the etching solution (e.g., which would lead to a break in the signal line formed on the intersection portion) can be prevented.
In a second aspect, a method for manufacturing a liquid crystal display panel according to the present invention includes forming a gate insulating film, a channel layer and an etching stopper layer on a transparent substrate bearing a gate electrode and the gate line, and exposing the substrate to light from its back surface side by using the gate electrode and the gate line as light shielding masks by a photolithography technique. Then, the resist is developed and the etching stopper layer is etched, and thereby an etching stopper is formed. Thus, the inventive manufacturing method forms an etching stopper using a single-stage exposing step.
Further, two or more conductive portions and one or more opening portions are formed on the intersection portion of the gate line where the gate line and the signal line intersect each other, and the resist is removed from the opening portion. During the etching step of forming the etching stopper layer, since the etching stopper layer is also etched from the opening portion side, and since the etching stopper layer near (e.g., adjacent) the opening portion is also etched by the side-etching effect, the etching stopper layer is removed from the intersection portion.
In the liquid crystal display panel and the method for manufacturing the same according to the present invention, the exposing step of forming the etching stopper layer includes only one step in which the gate electrode and the gate line are used as shielding masks. Since the inventive manufacturing method does not include a time-consuming exposing step in which a shielding mask, such as a reticle, is used and a high precision positioning of the shielding mask is required, productivity is dramatically increased.
The present disclosure relates to subject matter contained in Japanese Patent Application No. 11-034227, filed Feb. 12, 1999, which is expressly incorporated herein by reference in its entirety.